使用VHDL語言實現 I²C協定，用來控制 PCA9685 (VHDL篇)－肯特王的簿

PCA9685是一個 I²C 協定控制的16通道PWM輸出IC，這顆IC原本被設計應用在RGBA彩色背光等LED亮度控制上，因其頻率的可編程範圍為24~1526Hz，含蓋了伺服馬達控制的50Hz，聰明的創客們便用它來擴充伺服的控制數量。

這篇文章主要以"VHDL語言撰寫控制PCA9685的程式碼"介紹為主，首先將全部程式碼顯示於下，接著再來看各程式碼的作用

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity PCA9685 is
port( CLK : in std_logic;
Start : in std_logic;
Addr : in std_logic_vector(5 downto 0);
RegAddr : in std_logic_vector(7 downto 0);
RegData : in std_logic_vector(7 downto 0);
SDA : inout std_logic;
SCL : out std_logic;
NoACK : buffer std_logic;
Complete : buffer std_logic);
end PCA9685;

architecture ARCH of PCA9685 is
constant indexStartCondition : integer := 0;
constant indexActive : integer := 10;
constant indexStopCondition : integer := 20;

signal index : integer;
signal delayCnt : integer;
signal bitN : integer;
signal exIndex : integer;
signal exAddr : std_logic_vector(7 downto 0);

begin
process(Start, CLK, index)
begin
if Start = '0' then
SDA <= '1';
SCL <= '1';
NoACK <= '0';
Complete <= '0';

index <= 0;
delayCnt <= 0;
bitN <= 7;
exIndex <= 0;
exAddr <= '1' & Addr & '0';

elsif CLK'event and CLK = '1' then
if Complete = '0' then
case index is
when (indexStartCondition + 0) =>
if delayCnt >= 29 then
delayCnt <= 0;
index <= index + 1;
else
delayCnt <= delayCnt + 1;
end if;
when (indexStartCondition + 1) =>
SDA <= '0';
index <= index + 1;
when (indexStartCondition + 2) =>
if delayCnt >= 14 then
delayCnt <= 0;
index <= index + 1;
else
delayCnt <= delayCnt + 1;
end if;
when (indexStartCondition + 3) =>
index <= indexActive;
--==============================================================================

when (indexActive + 0) =>
SCL <= '0';
index <= index + 1;
when (indexActive + 1) =>
if bitN < 0 then
SDA <= 'Z';
elsif exIndex = 0 then
SDA <= exAddr(bitN);
elsif exIndex = 1 then
SDA <= RegAddr(bitN);
else
SDA <= RegData(bitN);
end if;
index <= index + 1;
when (indexActive + 2) =>
if delayCnt >= 29 then
delayCnt <= 0;
index <= index + 1;
else
delayCnt <= delayCnt + 1;
end if;
when (indexActive + 3) =>
SCL <= '1';
index <= index + 1;
if bitN < 0 then
NoACK <= SDA;
end if;
when (indexActive + 4) =>
if delayCnt >= 29 then
delayCnt <= 0;
index <= index + 1;
else
delayCnt <= delayCnt + 1;
end if;
when (indexActive + 5) =>
if bitN = -1 then
bitN <= 7;
index <= index + 1;
else
bitN <= bitN - 1;
index <= (indexActive + 0);
end if;
when (indexActive + 6) =>
if exIndex = 2 then
exIndex <= 0;
index <= indexStopCondition;
else
exIndex <= exIndex + 1;
index <= (indexActive + 0);
end if;
--==============================================================================

when (indexStopCondition + 0) =>
SCL <= '0';
SDA <= '0';
index <= index + 1;
when (indexStopCondition + 1) =>
if delayCnt >= 29 then
delayCnt <= 0;
index <= index + 1;
else
delayCnt <= delayCnt + 1;
end if;
when (indexStopCondition + 2) =>
SCL <= '1';
index <= index + 1;
when (indexStopCondition + 3) =>
if delayCnt >= 14 then
delayCnt <= 0;
index <= index + 1;
else
delayCnt <= delayCnt + 1;
end if;
when (indexStopCondition + 4) =>
SDA <= '1';
Complete <= '1';
--==============================================================================

when others => null;
end case;
end if;
end if;
end process;
end ARCH;